If you declare multiple dimensional array as IO in verilog module, Vivado ERROR:
[VRFC 10-1243] port *** must not be declared to be an array [***********]
If dut is in Verilog and testbench is in SystemVerilog. Packed array can be used to pass data to/from DUT:flattened_array.
The GOCHA here when using packed array, signed attribute is tricky, packed array only respect signedness as whole not array elements. (see)
You might have your internal processing in signed math while using signed unpacked array is convenient.
To make the code working for both logic connect and signed math; you should define two logic variables:
- logic [x:0][y:0] wire_packed; // net used to connect to DUT flattened array
- logic signed [y:0] sig_unpacked; // signal used for signed math
Now the questions is, can you assign unpacked directly to packed. The answer is no:
assign wire_packed[n] = sig_unpacked[n];
[VRFC 10-395] cannot assign an unpacked type to a packed type [**************]
You have to use process:
/* unpacked to packed passing */
genvar idx;
generate
for (idx=2; idx>=0; idx=idx-1) begin
always @* begin : unpacked_to_packed_proc
wire_packed[idx] = sig_unpacked[idx];
end //always @*
end
endgenerate
After passing value. You can connect wire_packed as whole to your dut:multiple dimension array I/O port.